1. Field of the invention
The present invention relates, in general, to a lightly doped drain (hereinafter "LDD") transistor and a method for the fabrication of the same, and more particularly, to improvements in source/drain junction breakdown voltage and junction leakage current.
2. Description of the Prior Art
Generally, as a semiconductor device becomes highly integrated, the integration degree of chip is increased and the channel of the transistor becomes shorten. The reduction of channel length causes problems such as drain-induced barrier lowering (hereinafter "DIBL"), hot carrier effect and short channel effect.
In order to solve these problems, a transistor which has an LDD structure has been proposed.
Hereinafter, description for a conventional LDD transistor is to be given for the better understanding of the prior art with reference to a few figures, wherein reference numeral 1 designates a silicon substrate whereas reference numerals 2, 3, 4, 5, 6, 6', 7, 8, 20, 30, 40 and 50 designate a field oxide film, a gate electrode, gate polyoxide film, an LDD region (or low density ion-implanted region), an oxide film, spacer oxide film, a high density ion-implanted region, an interlayer insulating film, an operating region mask, a gate electrode mask, an N.sup.+ /P.sup.+ source/drain ion-implanting mask and a contact mask, respectively.
Referring initially to FIG. 1, there is a plan view showing only important mask layers required to fabricate a conventional LDD MOSFET. As shown in FIG. 1, an operational region mask 20 is used to form an operational region on a semiconductor substrate in advance of forming a gate electrode on a field oxide film by use of a gate electrode 30. Thereafter, an N.sup.+ /P.sup.+ source/drain ion-implanted mask 40 covering the operational region mask is utilized in order to form a high density N.sup.+ /P.sup.+ source/drain ion-implanted region, followed by the formation of a contact mask 50 for a contact hole.
Referring now to FIGS. 2A through 2D, there are cross-sectional views illustrating the fabrication steps for the conventional LDD MOSFET, taken generally through section line A--A' of FIG. 1, respectively.
First, FIG. 2A shows a silicon substrate having a P-well (or an N-well) which is sectioned by the formation of a field oxide film 2 into device separation region and an operational region, a gate electrode 3 covered with a gate polyoxide film 4 which is atop a gate oxide film (not shown) formed over the field oxide film 2, an LDD region 5 formed in the operational region and a blanket oxide film 6 which covers the resulting structure including bird's beak effected by the field oxide films 2.
The blanket oxide film 6 is subsequently subjected to an anisotropic etch process to form a spacer oxide film 6' and high density N.sup.+ (or P.sup.+) type impurities are, as indicated by arrows, implanted to form a high density N.sup.+ (or P.sup.+) ion-implanted source/drain region 7, as shown in FIG. 2B.
Next, a back thermal treatment process is applied for diffusing the LDD region 5 and the high density ion-implanted source/drain region 7 in the silicon substrate 1, as shown in FIG. 2C.
In the meanwhile, the reference mark A of the FIG. 3C designates a disadvantageous portion. That is, when the anisotropic etch process is applied to the blanket oxide film 6 so as to form the spacer oxide film 6', the bird's beak of the field oxide film 2 is partially etched at the portion intersected by the field oxide film 2, the gate electrode 3 and the operational region so as to injure the edge portion of the LDD region 5 which is worse deteriorated by the great density difference between the substrate 1 and the high density ion-implanted region 7.
Finally, FIG. 2D illustrates the process of forming a contact hole. For this, an interlayer insulating film 8 is entirely formed over the structure of FIG. 2C and then, subjected to a patterning process using a photosensitive material as a contact mask. Following that, an etch process is applied to the blanket interlayer insulating film 8 atop the operational region.
The above conventional LDD gate MOSFET comes to have the bird's beak which is partially removed at the intersectional portion among the gate electrode, the field oxide film and the operational region when carrying out the anisotropic etch process, so that the low density N.sup.- (or P.sup.-) LDD region gets damaged at its edge portion. What is worse, the low density N.sup.- (or P.sup.-) LDD region suffers from more damage caused by the great density difference between the high density N.sup.+ (or P.sup.+) ion-implanted source/drain region and the semiconductor substrate.
Such phenomena effect problems such as the weakening of source/drain junction breakdown voltage and the increase of junction leakage current.